1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit and, more particularly, to a receiver circuit of a semiconductor integrated circuit.
2. Related Art
Generally, an input receiver is employed as an interface circuit in a conventional semiconductor device such as a semiconductor memory. The input receiver plays an important role in signal transmission to receive and buffer an input signal from an external circuit and to transfer the input signal internally. Operational parameters such as the voltage level and set-up/hold time for the input receiver are critical factors to determine high-speed response characteristics of the input receiver and ultimately the device.
FIG. 1 is a block diagram illustrating a conventional receiver circuit. Referring to FIG. 1, the conventional receiver circuit includes a first digital-to-analog converter 1, a second digital-to-analog converter 2, a sense amplifier 4, and a latch unit 5.
The first digital-to-analog converter 1 receives a first control signal ‘CNT1<0:N>’ and then outputs eye monitoring voltages EMC+ and EMC−. The second digital-to-analog converter 2 outputs off-set control voltages OCC+ and OCC− in response to a second control signal ‘CNT2<0:N>’.
The sense amplifier 4 senses and amplifies input data ‘DATA+’ and ‘DATA−’ according to a clock signal ‘CLK’. The latch unit 5 latches output signals ‘SA_OUT’ and ‘SA_OUTB’ of the sense amplifier 4 to output a receiving data signal ‘RXDATA’.
The operation of the receiver circuit of FIG. 1 will now be discussed in detail. First, during an eye monitoring test, the first digital-to-analog converter 1 is driven and the eye monitoring voltages EMC+ and EMC− are output. The sense amplifier 4 senses and amplifies the input data ‘DATA+’ and ‘DATA−’ according to an off-set voltage that is controlled by the eye monitoring voltages EMC+ and EMC−.
When not in an eye monitoring test mode, the second digital-to-analog converter 2 is driven and the off-set control voltages OCC+ and OCC− are output. The sense amplifier 4 senses and amplifies the input data ‘DATA+’ and ‘DATA−’ according to an off-set voltage that is controlled by the off-set control voltages OCC+ and OCC−.
For example, if the eye monitoring voltages EMC+ and EMC− are in a range of a few hundreds of mV, the off-set control voltages OCC+ and OCC− are in a range of a few tens of mV.
The eye monitoring test is used for verifying that data transmitted from a transmission side, the transmitter, are correctly received by a receiving side, the receiver circuit. The accuracy of the data transmission can be verified by monitoring the result of overlay parts of the data outputs, i.e., by monitoring the data eye, through the eye monitoring test. The amount of jitter as well as the data eye can be verified through the eye monitoring test.
Because off-set voltages required in the sense amplifier 4 have different ranges depending on the mode of operation, the first and second digital-to-analog converters 1 and 2 are selectively driven according to the operating modes.
FIG. 2 is a circuit diagram illustrating the sense amplifier 4 included in the conventional receiver circuit of FIG. 1. Referring to FIG. 2, the sense amplifier 4 includes an input data amplifier 6, a first off-set voltage adjust unit 8, and a second off-set voltage adjust unit 7. The input data amplifier 6 is made of a cross-coupled latch circuit. The input data amplifier 6 senses and amplifies the input data ‘DATA+’ and ‘DATA−’ according to the clock signal ‘clk’. The first off-set voltage adjust unit 8 receives the eye monitoring voltages EMC+ and EMC− from the first digital-to-analog converter 1 and then controls the off-set voltage of the input data amplifier 6. The second off-set voltage adjust unit 7 receives the off-set control voltages OCC+ and OCC− from the second digital-to-analog converter 2 and then controls the off-set voltage of the input data amplifier 6.
the sense amplifier 4 can suffer, however, from nonlinear characteristics because of a mismatch (for example, size or area) between an input transistor and the differential drain current and input voltage applied thereto. Accordingly, in order to avoid this problem, the number of transistors is increased in the first off-set voltage adjust unit 8 and the second off-set voltage adjust unit 7 in the sense amplifier, which increases the resource overhead, and as a result, the clock loading is more severe because of increased signal routing due to the additional transistors.
As described above, the conventional receiver circuit uses two or more digital-to-analog converters, such as the first and second digital-to-analog converters 1 and 2, to output the off-set voltages in different ranges. Further, the sense amplifier 4 includes the first off-set voltage adjust unit 8, which receives the output signals of the first digital-to-analog converter 1, and the second off-set voltage adjust unit 7, which receives the output signals of the second digital-to-analog converter 2.
Accordingly, the sense amplifier 4 increases the resources required, and therefore the overhead and circuit area, of the conventional receiver circuit.